1. Field of the Invention
The present invention relates in general to a stabilization technique in a constant voltage generating circuit. More particularly, the present invention relates to a technique for receiving the first and second potentials to output an output voltage, and lessening a dependency upon a variation of the second potential.
2. Description of the Background Art
FIG. 10 is a circuit diagram showing a configuration a bias circuit 100 which is an example of a background art constant voltage generating circuit. In the figure, transistors T.sub.1 and T.sub.2 are NPN-type BJTs (Bipolar Junction Transistors). The collector of the transistor T.sub.1 is connected through a resistor R.sub.2 (hereinafter, the resistance of the resistor R.sub.2 is also represented as R.sub.2, and the same rule applies correspondingly to the following) to the first power supply line V.sub.CC (hereinafter, the potential to be provided as the first potential by the first power supply line V.sub.CC is also represented as V.sub.CC). The emitter of the transistor T.sub.1 is connected through a resistor R.sub.1 to the second power supply line V.sub.EE (hereinafter, the potential to be provided as the second potential by the second power supply line V.sub.EE is also represented as V.sub.EE). For example, the first potential V.sub.CC is set to 0V and the second potential V.sub.EE is set to negative potential of ECL level.
On the other hand, in the transistor T.sub.2, the collector is connected directly to the first power supply line V.sub.CC, the emitter is connected through a resistor R.sub.3 to the second power supply line V.sub.EE and the base is connected the collector of the transistor T.sub.1. The base of the transistor T.sub.1 and an output terminal are connected to the emitter of the transistor T.sub.2.
The output terminal receives an output potential V.sub.O to output the potential difference between the output potential V.sub.O and the second potential V.sub.EE as an output potential V.sub.CS.
The operation of the bias circuit 100 having the aforementioned configuration will be described. The collector of the transistor T.sub.1, the resistor R.sub.2 and the base of the transistor T.sub.2 are connected at a node A and the emitter of the transistor T.sub.1 and the resistor R.sub.1 are connected at a node B. Representing the potential of the node B as V.sub.B, the following relation is satisfied: EQU V.sub.O =V.sub.B +V.sub.1 ( 1)
Assuming now that the base-emitter voltages of the transistors T.sub.1 and T.sub.2 are V.sub.1 and V.sub.2, respectively, in disregard of the base currents of the transistors T.sub.1 and T.sub.2, Formula (1) is transformed into the following expression: ##EQU1##
Preferably, the output voltage, V.sub.CS =V.sub.O -V.sub.EE, is always constant. Taking a case where the bias circuit 100 is connected to an ECL circuit by way of example, the reason will be described below.
FIG. 11 is a circuit diagram showing a configuration of the ECL circuit Q.sub.9 connected to the bias circuit 100 and connection of these two circuits. This figure shows the employment of an inverter as the ECL circuit Q.sub.9. The ECL circuit Q.sub.9 comprises a transistor T.sub.11 the base of which receives an input signal, a transistor T.sub.12 a base of which receives a fixed potential V.sub.BB and a current source Q.sub.10 connected common to the emitters of the transistors T.sub.11 and T.sub.12, drawing a current out of these transistors into the power supply line V.sub.EE. The collectors of the transistors T.sub.11 and T.sub.12 are connected through respective resistors to the first power supply line V.sub.CC.
The current source Q.sub.10 comprises a transistor T.sub.10 a collector of which is connected in common to the emitters of the transistors T.sub.11 and T.sub.12 and a base of which receives the output potential V.sub.O of the bias circuit 100 and a resistor R.sub.10 connecting the emitter of the transistor T.sub.10 with the second power supply line V.sub.EE.
When the output potential V.sub.CS varies, the current from the current source Q.sub.10 accordingly varies, so that it cannot remain constant. That causes malfunction of the ECL circuit Q.sub.9. Therefore, in order to stabilize the operation of ECL circuit Q.sub.9 which is connected to the bias circuit 100, it is desirable to keep the output voltage, V.sub.CS =V.sub.O -V.sub.EE, always at a constant value.
On the other hand, the variation of the output voltage V.sub.CS is caused by the variations of the first and second potentials V.sub.CC and V.sub.EE. Let us consider now a case where the first potential V.sub.CC is fixed to 0V without variation and the second potential V.sub.EE having negative value may vary.
The dependency of the output voltage V.sub.CS upon the second potential V.sub.EE can be obtained from Formula (2) as follows: ##EQU2##
Since the first potential V.sub.CC is fixed to 0 V without variation, the following formula is obtained: ##EQU3##
In this formula, the first term on the right-hand side represents the dependency of the base-emitter voltages V.sub.1 and V.sub.2 of the transistors T.sub.1 and T.sub.2 upon the second potential V.sub.EE which is approximately negligible in comparison with the second term.
On the other hand, since R.sub.2 /R.sub.1 is usually determined to around 1 in order to make the temperature dependency of the output voltage V.sub.CS low, even if the first term on the right-hand side is negligible, the dependency of the output voltage V.sub.CS upon the second potential V.sub.EE is expressed as follows: ##EQU4##
Since the background art bias circuit 100 has the aforementioned configuration, when the second potential V.sub.EE which is lower than the first potential varies, the output voltage V.sub.CS also varies in proportion to the variation of the second potential V.sub.EE. For this reason, there arises a problem of causing malfunction of the ECL circuit Q.sub.9 connected to the bias circuit 100.